Exemplary embodiments of the present invention relate to a semiconductor memory device and a fabrication method thereof, and more particularly, to a non-volatile memory device having a three-dimensional (3D) structure, and a method for fabricating the non-volatile memory device.
A non-volatile memory device is a memory device which stores data even if power supply is cut off. As the integration degree of a two-dimensional memory device, which is fabricated in the form of layers over a silicon substrate, is reaching limits, a non-volatile memory device having a 3D structure in which memory cells are stacked vertically from a silicon substrate have been developed.
Hereafter, a structure of a conventional 3D non-volatile memory device and related concerns will be described in detail with reference to the drawings.
FIG. 1 is a cross-sectional view showing a structure of a conventional 3D non-volatile memory device having vertical channels, and a fabrication method thereof.
Referring to FIG. 1, a plurality of first inter-layer dielectric layers 11 and a first gate electrode 12 are formed over a substrate 10 having a source region defined therein, and a trench is formed to expose the surface of the substrate 10 by etching the first inter-layer dielectric layers 11 and the first gate electrode 12. Subsequently, after a first gate insulation layer 13 is formed on the internal walls of the trench, a channel CH is formed by filling the trench with a channel-forming layer. As a result, a lower select transistor LST is formed.
Subsequently, a plurality of second inter-layer dielectric layers 14 and a plurality of second gate electrode 15 are formed over the substrate structure where the lower select transistor LST is formed. Here, the number of the stacked second inter-layer dielectric layers 14 and the number of the stacked second gate electrode 15 are decided based on the number of memory cells to be stacked.
Subsequently, the plurality of the second inter-layer dielectric layers 14 and the plurality of the second gate electrode 15 are etched to form a trench that exposes a channel CH of the lower select transistor (LST). Subsequently, a charge blocking layer, a charge trapping layer, and a tunnel insulation layer (see reference numeral ‘16’) are sequentially formed on the internal walls of the trench. As a result, a plurality of memory cells MC are formed.
Subsequently, a plurality of third inter-layer dielectric layers 17 and a third gate electrode 18 are formed over the plurality of the memory cells MC, and they are etched to form a trench that exposes a channel of a memory cell MC. Subsequently, a second gate insulation layer 19 is formed on the internal walls of the trench, and a channel CH is formed by filling the trench with a channel-forming layer. As a result, an upper select transistor (UST) is formed.
Here, the plurality of the memory cells MC are serially connected between the lower select transistor (LST) and the upper select transistor (UST) to form one string.
According to the above described conventional methods, the degree of integration may be improved over a conventional flat non-volatile memory device by arranging strings vertically from the substrate 10. When the strings are arranged vertically, the number of stacked memory cells may be increased to enhance the degree of integration even more, but such an increase in the number of stacked memory cells is becoming more difficult to achieve.
Further, according to the above described conventional methods, after a lower select transistor (LST) is formed, memory cells and an upper select transistor (UST) are sequentially formed. Thus, three steps are performed to form a string. Such steps complicate the fabrication process and increase production costs.